In the past, performance of LSIs has been improved with advance of technology nodes by design shrinkage in accordance with a scaling law along with Moore's Law. Although 20-nm nodes and 14-nm nodes are currently under development, it is imperative to suppress short-channel characteristics of transistors. For example, degradation of the short-channel characteristics may cause an increase in a leakage current due to subthreshold leakage during standby. The leakage current is a major issue specifically in SRAMs and other memories. In recent years, an urgent task is therefore to reduce power consumption by replacement of volatile memories with non-volatile memories, and various kinds of non-volatile memories are under development. In particular, expectations are growing for spin transfer torque-magnetic tunnel junctions (STT-MTJs) that allows for high-speed writing and reading.
For high-speed writing, it is important to improve performance of select transistors. In general, responsiveness of writing and retention characteristics are in a trade-off relationship. Accordingly, application of a transistor having high performance makes it possible to select a material having high retention characteristics as a material of the MTJs, thereby securing performance stability as memories as well.
In order to improve transistor characteristics, for example, there is proposed in Patent Literature 1 that a channel of a transistor is provided in a direction perpendicular to a substrate surface.